Low speed, load independent, slew rate controlled output buffer with no dc power consumption

ABSTRACT

An output buffer utilizes capacitive feedback to control the output slew rate largely independent of load capacitance. The invention slows the rising and falling slew rates and via a capacitance feedback reduces the effect of load capacitance on slew rate, and uses no DC current. Transistor switches are employed to isolate and reduce noise and interaction among the circuit components and functions.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to CMOS output buffers, and moreparticularly to output buffers with controlled slow slew rates that arerelatively independent of capacitive loads and draw no DC power.

2. Background Information

Output buffers must be fast enough to match the high data rates of thesignals the buffer is sending, but they must be slow enough to not causeEMI (ElectroMagnetic Interference) with nearby electronics. “Fastenough” and “slow enough” refers to the speed of rising and fallingedges. Slew rates,” edge “rise and fall times,” and other such terms asmay be used in the art may have different definitions, but they are usedinterchangeably herein.

Output load capacitance has a substantial effect of slew rates. With a20/1 capacitive load variation, prior art slew rates may varyproportionally or even more depending on the equivalent resistanceoperating with the load capacitance.

FIG. 1 illustrates a prior art output buffer's voltage profiles with 10pF, 75 pF and 150 pF capacitive loads. So, for example, if a square waveis input, the output edge rise and fall times 10 are about onenanosecond with a 10 pF load capacitor, and those times increase totwenty-four nanoseconds with a 150 pF load capacitor. In this example a15 to 1 increase in output capacitance results in a 24 to 1 edge slowdown.

Limitations of the prior art include one nano-second edge times that maygenerate EMI noise adversely affecting other electronics, and, withlarge load capacitors, slow edge rise and fall times may not meet thedata rates of the signals involved.

U.S. Pat. No. 5,748,019 ('019) owned by VLSI Technologies, Inc. of SanJose, Calif. compensates for load capacitance. The '019 reference,however, uses reference voltage supplies, current sources and capacitivefeedback. But the '019 use voltage references, that constantly drain DCcurrent, and capacitors and current sources that distinguish thisreference from the present invention.

It would be advantageous to have an output buffer with an output edgetime that remained about constant with capacitive load variations; thatwas slow enough to not cause EMI disturbances, but was fast enough tomeet the data rates of the circuitry involved. For example, an outputbuffer with an edge rising and falling time of about 20 to 40nanoseconds when loaded with 10 to 200 pF capacitors, respectively.

SUMMARY OF THE INVENTION

The present invention provides a capacitive feedback circuit thatsubstantially reduces, with respect to prior art, slew rate variationswhen the capacitive load varies substantially.

Separate RC (Resistor/Capacitor) networks are formed for both positiveand negative voltage edges at the output of the buffer. These RC's arearranged to provide a negative feed back to control the slew ratesrelatively independent of the load capacitors.

Illustratively, the present invention provides for a single inverterinput and the charging and discharging of load capacitors and thefeedback capacitors through the same output transistor. Current throughthe feedback capacitor to the gate or control input of the outputtransistor slows the turn on of the output transistor, reduces thecurrent to the load capacitor thereby slowing the edge rise and falltimes of the output voltage. The net effect is to make the slew raterelatively independent of the load capacitors. One way of describing theeffect is that the feedback current is dependent upon the loadcapacitance current. As more load current is delivered, a negativefeedback current reduces the rate of increase of load current.

Illustratively, the present invention employs a combination of PMOS andparallel “native NMOS transistors” as the feedback capacitors. Thisembodiment provides cleaner output rise and fall times. Herein a “nativeNMOS transistor” refers to a an NMOS transistor that has not undergonechannel doping. Such transistors have lower threshold voltages (usually0 to 3V, or even negative) because it must rely on the intrinsicbackground or body of the transistor to set the threshold voltage.Because the threshold voltage is lower, a native device provides abetter capacitor with a wider voltage range.

It will be appreciated by those skilled in the art that although thefollowing Detailed Description will proceed with reference being made toillustrative embodiments, the drawings, and methods of use, the presentinvention is not intended to be limited to these embodiments and methodsof use. Rather, the present invention is of broad scope and is intendedto be defined as only set forth in the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention description below refers to the accompanying drawings, ofwhich:

FIG. 1 is a timing diagram of a prior art output buffer response;

FIG. 2 is a schematic illustrating the feedback character of the presentinvention;

FIG. 3 is a more detailed schematic illustrating the present invention;

FIG. 4 is a timing diagram of the circuit of FIG. 3 output bufferresponse; and

FIG. 5 is a timing chart illustrating a transition area of the circuitof FIG. 3.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

FIG. 2A is a simplified schematic illustrating a capacitive feedbackcircuit embodiment of the present invention. FIG. 2B is the associatedtiming diagram.

With Vin low 26, V2 is high and P2 on driving Va high and keeping P1off. Vb is high turning on N1 that drives Vout low. When Vin goes high28, V2 goes low, and N2 turns on, drives Vb low and turns N1 off. Iprises drawing current from Cp, Cn and Cl, and Va starts to fall 30.Since P1 is not yet on Id is delayed 21, and Vout falls slightly 20 assome of Ip is taken from Cl.

Va falls to a point 22 where P1 starts to turn on supplying Id. Idcharges Cl and Vout rises 24. As Vout rises some of Id flows through Cpto Va. This feedback action slows the fall of Va, slows the turn on ofP1 and the rise if Id. Note that as Vout rises some of Id is divertedthrough Cn. Nonetheless, Vout rises more slowly but with more controland less dependence on Cl than in prior art buffers. Using other words,the feedback operation operates as follows, if Cl is larger, with thesame Id current, Vout will rise more slowly thereby driving less currentthrough Cp. Va falls more quickly, turning on P1 more quickly andincreasing Id to charge Cl more quickly. If Cl is smaller, Cl chargesmore quickly, Va rises more quickly slowing the turn on of P1 andslowing the rise of Id and the charging of Cl.

When Vin goes back low 31, P1 is turned off via P2 and N2 is turned offallowing N1 to turn on. Vb is low and starts going high 32. As Vb risesit drives current through Cn, Cp and Cl where Vout rises 34 slightly.The turn on of N1 is delayed 33, but at point 36 N1 starts to turn onsupplying In to drive Vout low 38. Here the low going Vout draws currentfrom Vb via Cn and slows the rise of Vb and thus the turn on of N1. theoperation is similar to that for the rising Vout as described before.

FIG. 3A is a more detailed schematic of the base circuit of FIG. 2A. Theadditions in FIG. 3A are: the Sp switch that connect Rp to P1 gate whenVin goes high; and the Sn switch that connects Rn to N1 gate when Vin islow. As shown in FIG. 3B, the capacitors Cp and Cn are each formed froma combination of a P and a native N type CMOS transistor.

In other embodiments the Cp and Cn capacitors may be of virtually anystructure, e.g. from a capacitor, not formed from a diode or transistor,but from electrodes separated by a dielectric. Other examples of Cp andCn include: a single or multiple PMOS structures; a single or multipleNMOS structures; any combination of PMOS and non-native NMOS structures;reciprocally connected PMOS and NMOS (NMOS gate to PMOS source/drain,PMOS gate to NMOS source/drain, and other such combination); and even insome embodiments reverse biased bipolar structures.

The output transistors P1 and N1 are isolated by the Sp and Sn switches,and held off by P2 and N2, thereby isolating the output transistors P1and N1 from each other virtually eliminating any “crowbar” current.Moreover, the circuit draws no DC current since there are no DC currentpaths.

FIG. 4 shows the output buffer response of the circuit of FIG. 3A, 3Bwith a square wave voltage input and load capacitors of 10 pF trace 40,75 pF, trace 42, and 150 pF, trace 44. The corresponding rise times are17 nanoseconds for trace 40 to 37 nanoseconds for trace 44.

FIG. 5 illustrates a rising edge of the Vout and the falling edge Va (atthe gate of P1) as P1 turns on at 22 producing current Id. Note the dipin Vout 20 where P2 is not yet on, and current is first drawn via Cpfrom Cl. The circled part is where Il about equals Icp.

It should be understood that above-described embodiments are beingpresented herein as examples and that many variations and alternativesthereof are possible. Accordingly, the present invention should beviewed broadly as being defined only as set forth in the hereinafterappended claims.

1. An output buffer comprising: an inverter with an input connected toan input signal, the inverter defining an inverter output; a pull upoutput transistor with its drain connected to a signal output; aresistor with one end connected to the inverter output and the other endconnected to the gate of the pull up transistor; a feedback capacitorconnected between the gate of the pull up transistor and the signaloutput; wherein when the input signal goes high, the inverter outputgoes low and the gate voltage starts to go low turning on the pull upoutput transistor, the signal output starts to go high, wherein thesignal output going high drives current through the feedback capacitorthereby slowing the fall of the gate voltage and slows the rises of thesignal output, and wherein the output buffer uses no DC current.
 2. Theoutput buffer of claim 1 further comprising: a pull down transistor withits drain connected to the output; a second resistor with one endconnected to the inverter output and the other end connected to the gateof the pull down transistor; a second feedback capacitor connectedbetween the gate of the pull down transistor and the output; whereinwhen the inverter output goes high, the gate voltage starts to go highturning on the pull down output transistor, the signal output starts togo low, wherein the signal output going low drives current through thesecond feedback capacitor thereby slowing the rise of the pull downtransistor gate voltage and slows the fall of the signal output.
 3. Theoutput buffer of claim 2 further comprising: a third transistor with itssource connected to a power supply, its gate connected to the inputsignal, and its drain to the gate of the pull up transistor, whereinwhen the input signal goes high, the third transistor is tuned on andturns off the pull up transistor; and a fourth transistor with itssource connected to a ground, its gate connected to the input signal,and its drain to the gate of the pull down transistor, wherein when theinput signal goes low, the fourth transistor is tuned on and turns offthe pull down transistor.
 4. The output buffer of claim 3 furthercomprising a first switch connected between the gate of the pull upoutput transistor and the feedback capacitor and the end of theresistor, wherein the switch is turned on when the inverter output goeslow and off when the inverter output goes high, and a second switchconnected between the gate of the pull down output transistor and thesecond feedback capacitor and the end of the second resistor, whereinthe switch is turned on when the inverter output goes high and off whenthe inverter output goes low.
 5. The output buffer of claim 2 whereinthe feedback capacitor and the second feedback capacitor both comprisecombinational PMOS and a parallel NMOS transistors.
 6. A method forcontrolling the edge rise and fall times of an output, the methodcomprising the steps of: inverting an input signal and producing aninverter output; driving the gate from the inverter output and turningon a pull up transistor via a resistor driving the output from the drainof the pull up output transistor; feeding back the output via acapacitor connected to the gate of the pull up transistor; wherein whenthe feedback operates to counter the inverter output, and wherein no DCcurrent is used.
 7. The method of claim 6 further comprising the stepsof: driving the gate from the inverter output and turning on a pull downtransistor via a second resistor; driving the output from the drain ofthe second transistor; second feeding back the output via a secondcapacitor connected to the gate of the pull down transistor, wherein thesecond feedback operated to counter the inverter output.
 8. The methodof claim 7 further comprising the steps of: turning on a thirdtransistor from the input signal, wherein when the third transistorturns on it turns off the pull up transistor; and turning on a fourthtransistor from the input signal, wherein when the fourth transistorturns on it turns off the pull down transistor.
 9. The method of claim 8further comprising the steps of: disconnecting the gate of the pull upoutput transistor from the feedback capacitor and the resistor when thepull down transistor is being turned on; and, disconnecting the gate ofthe pull down output transistor from the second feedback capacitor andthe second resistor when the pull up transistor is being turned on.